Tower Semiconductor - Powering AI From Orbit (Pt.5)

Tower Semiconductor - Powering AI From Orbit (Pt.5)

Tower's SiGe BiCMOS + SiPho platform on 300mm wafers eliminates GFS's sole advantage, delivers 30% lower power than InP at 1/3 the cost with 85%+ yields, and cements TSEM as the dominant SiPh foundry for both hyperscale AI and Space DC deployments.

Summary

• Silicon photonics is displacing InP as the dominant optical interconnect platform — Tower's new SBC18H6 node reverses SiPh's historical power penalty, delivering ~30% lower power than InP EMLs while enabling 112G PAM4 for 1.6T/3.2T transceivers.

• Tower's PH18 is the de facto fabless SiPh standard, with ecosystem lock-in that is structurally unbreakable because photonic designs cannot be ported between foundries without full redesign — and its OFC 2026 300 mm announcement eliminated GFS's sole differentiator.

  
  

• Manufactured on 300 mm wafers with 85%+ yields at roughly one-third the cost of InP, with Broadcom and Marvell locking 70%+ of capacity and $900M+ in expansion underway.

• Tower is already space-qualified: radiation heritage (TID, SEL, proton irradiation), thermal stability, and deep ecosystem depth make it the only credible SiPh foundry for orbital deployment.

• With SpaceX now public and space-based AI data centers emerging as a capital-backed buildout thesis rather than a speculative concept, Tower's proven space qualification positions it as the foundry incumbent for what may become one of the decade's most significant infrastructure trends.

TSEM: Solidifying SiPh Leadership Over GFS

Tower Semiconductor operates what is arguably the most important foundry platform in silicon photonics today. Its PH18 process — an 180nm silicon-on-insulator platform purpose-built for integrating optical components like waveguides, modulators, and photodetectors onto a single chip — has become the de facto manufacturing standard for the fabless silicon photonics (SiPh) industry. Virtually every major fabless SiPh design house, including Ayar Labs, Lightmatter, and Ranovus, has built its design ecosystem around PH18. Their process design kits (PDK), design rules, yield models, and years of tapeout history are all tailored to this specific platform, creating an enormous degree of ecosystem lock-in.

What makes this lock-in so durable is that switching foundries in photonics is a fundamentally different proposition than switching in conventional digital chip design. In standard CMOS, a designer describes their chip's logic in abstract code and then uses software tools to "resynthesize" that logic onto a new foundry's process — somewhat like reformatting a document for a different printer. The logical design is portable even if the physical layout must change. In photonics, no such abstraction layer exists. The performance of every optical element — how much light a waveguide loses around a bend, how efficiently a modulator switches a signal, how sensitive a germanium detector is — is dictated by the precise physical geometry and material properties unique to a given foundry's process. Moving to a different foundry doesn't mean recompiling; it means redesigning from scratch, recharacterizing every component, and running through entirely new tapeout cycles. This is why Tower's incumbency with PH18 is not merely a commercial lead but a structural moat.

GlobalFoundries pitched its 300 mm Fotonix platform as the answer to this incumbency — arguing that the larger wafer format, yielding roughly 2.25x the die per wafer versus a 200 mm line, would drive cost per photonic integrated circuit down at high volume and lure customers away from Tower on economics alone. But even before Tower's OFC 2026 announcement eliminated this wafer-size argument entirely, the Fotonix thesis was failing on its own terms. The platform has been slow to ramp real production, the PDK is less mature, and the design ecosystem is thinner. The supposed cost advantage at scale remained theoretical because GFS never reached that scale — it lacked the customers running volume production to prove out the economics.

It is also worth understanding why the wafer-size argument was always structurally weaker in photonics than it would be in digital logic. In conventional digital chips, the march to more advanced lithography — from DUV to EUV, for instance — serves a dual purpose. It enables miniaturization, meaning physically smaller transistors, which is the whole point: you shrink the features so you can pack more of them into a given area, which is how each successive "node" delivers more performance per dollar. Tighter dimensional control comes along for the ride, but the economic engine is really about cramming more functionality onto every square millimeter of silicon. That is what makes a node shrink so transformative in digital — the chip can either get smaller and cheaper or stay the same size and become dramatically more powerful.

In photonics, this logic breaks down. The fundamental building blocks — waveguides, ring resonators, grating couplers — are sized to interact with light, and light has a fixed wavelength on the order of one to two micrometers. You cannot shrink a waveguide the way you shrink a transistor, because if you make it too small, the light simply will not propagate correctly. The components are the size they are because physics demands it, not because the lithography cannot do better. So what does advanced lithography buy you in photonics? Tighter dimensional control — meaning less variation from one waveguide to the next, less phase error, better uniformity across the wafer. These are real and meaningful improvements, but they are incremental refinements, not the kind of step-function economic transformation that a node shrink delivers in the digital world. GlobalFoundries' finer lithography helps at the margins, but it does not fundamentally reshape the cost equation the way moving from 7 nm to 3 nm reshapes the economics of a digital processor.

Whatever residual argument GFS had on wafer economics was then definitively closed at OFC 2026, when Tower announced its SiGe BiCMOS + Silicon Photonics platform manufactured on full 300 mm wafers. Tower now matches GFS on wafer format while retaining its overwhelming advantages in ecosystem maturity, customer lock-in, and production heritage. The competitive framing has shifted from "GFS has 300 mm and Tower does not" to "both have 300 mm, but only Tower has the customers, the PDK maturity, and the proven yield."

In the space context specifically, the gap widens further still. Tower has actual radiation test data on PH18 PICs — published papers demonstrating how the components hold up under the punishing conditions of orbit. This includes total ionizing dose tolerance, which measures whether a chip's performance degrades gracefully or catastrophically as it absorbs cumulative radiation over months and years in space, as well as single-event latchup characterization, which tests whether a single high-energy particle strike can cause a short circuit that locks up or destroys the chip. Tower has also published data on performance under proton irradiation, simulating the bombardment that components face from solar wind and cosmic rays. Multiple defense and space programs have already qualified PH18 components on the basis of this heritage. GlobalFoundries has essentially none of it for Fotonix. For a SpaceX engineer choosing a silicon photonics foundry for an optical terminal that must survive in very low Earth orbit for three to five years, the decision is trivial — it is Tower.

The honest assessment: GFS should be removed from the Space DC supply chain thesis entirely. It is not merely behind Tower in maturity — it has lost its only differentiated structural argument (wafer size), has no radiation heritage, no ecosystem depth, and no volume customers in this segment. Tower has the ecosystem, the heritage, the yield data, the customer base, and now the 300 mm manufacturing scale. There is no credible path by which GFS displaces Tower in the space optical interconnect market within any investable time horizon.

Bottom line: Tower is the SiPh foundry for the Space DC.

At OFC 2026, Tower dropped what may be the most consequential announcement of the conference: a new suite of SiGe BiCMOS + Silicon Photonics process innovations that collectively position the company at the epicenter of the next-generation optical interconnect buildout. The implications span performance, power, cost, and — critically — scalability, addressing nearly every bottleneck that has constrained high-end transceiver deployment to date.

The Process Node: SBC18H6

At the heart of the announcement is TSEM's latest SiGe BiCMOS process node, the SBC18H6. This node achieves Ft/Fmax figures in the range of 325 to 450 GHz, a level of high-frequency performance that enables stable, reliable support for 112 Gbaud PAM4 signaling — the modulation scheme underpinning both 1.6T and 3.2T optical transceiver architectures. Reaching these frequencies with stability and margin is non-trivial; it is the threshold at which the transceiver industry can confidently move beyond 800G and into the next generation of data rates without resorting to exotic and costly material platforms.

One of the most persistent criticisms of Silicon Photonics as a platform has been its power consumption relative to Indium Phosphide (InP)-based Electro-Absorption Modulated Lasers (EMLs). Historically, SiPho-based transceivers consumed 30% or more power than their InP EML counterparts while delivering inferior performance. TSEM's SiGe + SiPho integration flips this equation. The company is now demonstrating power consumption approximately 30% lower than equivalent InP solutions. This is a dramatic reversal — moving from a 30%+ power penalty to a 30% power advantage — and fundamentally changes the calculus for hyperscalers and system designers evaluating optical interconnect platforms for power-constrained AI and HPC environments.

The historical weakness of silicon photonics has not been the photonic waveguides or modulators themselves, but rather the inability to monolithically integrate the laser source and the high-performance analog electronics onto the same platform with sufficient performance. Two analog components are critical here: the transimpedance amplifier (TIA), which converts the faint photocurrent from a photodetector into a clean voltage signal on the receive side, and the laser driver, which delivers precisely shaped electrical signals to the on-chip optical modulator on the transmit side. In a silicon photonics transmit chain, the laser itself typically runs as a continuous light source — it is the modulator, sitting on the photonic chip in the laser's optical path, that encodes data onto that light by rapidly altering its phase or intensity. The laser driver must deliver these drive signals to the modulator with extreme precision and speed, making it every bit as demanding an analog design challenge as the TIA. Both are analog circuits that demand extremely low noise, wide bandwidth, and careful impedance matching — meaning the electrical interfaces between components must be precisely tuned so signals transfer cleanly rather than reflecting back and degrading performance — characteristics that are difficult to achieve on the same process used to fabricate photonic waveguides.

InP's architectural advantage was always that it could integrate the laser with the modulator in a single externally modulated laser package, creating a compact monolithic unit where light generation and signal modulation happened in one material system without the performance penalties of stitching together separate chips.

Tower's approach addresses this gap directly. Its SiGe BiCMOS process — a technology purpose-built for high-frequency analog circuits — serves as the analog engine, handling both the TIA and laser driver functions at the speeds demanded by 112G PAM4 signaling and beyond. SiGe BiCMOS is well suited to this role because its bipolar transistors offer the combination of high gain, low noise, and wide bandwidth that these analog functions require, in a way that standard digital CMOS processes cannot match. Crucially, the SiGe die can be hybrid bonded in a three-dimensional structure with the silicon photonic die, meaning the analog electronics sit directly atop the optical layer with extremely short, low-parasitic interconnects between them. The result is a tightly integrated photonic-electronic package where the analog circuitry performs nearly as if it were monolithically part of the photonic chip. The laser itself can then be co-packaged or bonded into this same stack. Taken together, this architecture closes the integration gap with InP EMLs — not by replicating InP's monolithic material advantage, but by achieving comparable system-level performance through intimate three-dimensional packaging of best-in-class components, each fabricated on the process most suited to its function.

A Natural Fit for Co-Packaged Optics (CPO)

The SiGe + SiPho platform aligns exceptionally well with emerging Co-Packaged Optics architectures, which aim to bring optical I/O directly onto or immediately adjacent to the switch or compute ASIC. Two properties of the TSEM platform stand out in this context.

First, thermal stability. Ring-resonator-based CPO approaches — notably the architecture favored by NVIDIA in its recent Foxconn-NPI-backed CPO program — are notoriously sensitive to temperature variations. Even small thermal fluctuations require active tuning and compensation, adding complexity and power overhead. TSEM's SiGe + SiPho platform, by contrast, demonstrates high stability across a wide operating temperature range, reducing or eliminating this sensitivity and simplifying the thermal management challenge in dense CPO deployments.

Second, radiation hardness. The platform is inherently radiation-tolerant, opening deployment in space, aerospace, and other high-reliability environments where InP or ring-based silicon photonic solutions face qualification challenges. While this is a secondary market consideration for hyperscale data centers, it broadens the total addressable market considerably and speaks to the fundamental robustness of the technology.

The Manufacturing Advantage: 300mm Silicon at

Scale

This is where the OFC 2026 announcement transitions from technically impressive to strategically transformative.

TSEM's SiGe + SiPho platform is manufactured on full 300mm silicon wafers, making it fully compatible with existing high-volume silicon manufacturing infrastructure. This stands in stark contrast to InP, which remains largely confined to 4-inch (100mm) wafers on specialty process lines — an order of magnitude less efficient in terms of die-per-wafer economics and fab utilization. The manufacturing implications cascade through every relevant metric.

Yield on TSEM's SiGe process exceeds 85%, compared to the 40–60% yield range typical of InP specialty nodes. When combined with the far larger wafer size, the effective cost-per-good-die advantage is enormous. TSEM estimates the resulting transceiver cost at roughly one-third that of equivalent InP-based solutions. This is not an incremental cost improvement; it is a structural cost reset that makes high-end optical transceivers dramatically more accessible at the volumes demanded by AI infrastructure buildouts.

The scalability profile mirrors that of standard silicon-based logic node ramp-ups — a production paradigm the semiconductor industry has spent decades perfecting. InP, by contrast, remains a craft-scale process with limited fab capacity globally and no clear path to comparable scaling.

TSEM's Strategic Position

TSEM controls an estimated 80% or more of high-end SiGe BiCMOS production globally, giving it a near-monopolistic position in this critical enabling technology layer. The company has already locked in commitments from Broadcom (AVGO) and Marvell (MRVL), with over 70% of available capacity reportedly contracted through 2028. These are the two dominant custom silicon and transceiver ASIC suppliers to the hyperscale market, and their early and aggressive capacity lockups signal deep confidence in the SiGe + SiPho roadmap.

TSEM is backing this demand signal with capital. The company is investing over $900 million in capacity expansion, targeting a roughly 5x increase in production output through 2026 and beyond. This level of investment — and the corresponding production ramp trajectory — would be unthinkable on an InP platform, where fab expansion is constrained by the limited supplier base for epitaxial wafers, the small wafer format, and the low yields that make capacity additions capital-inefficient.

Market Implications

With SiPho already commanding a significant share of the 800G transceiver market, TSEM's advancements suggest that silicon photonics penetration at 800G could exceed 85% by 2028, with the SiGe + SiPho stack increasingly displacing InP EML at the high end. As the industry transitions to 1.6T and 3.2T, the SiGe + SiPho platform appears positioned not merely as an alternative to InP, but as the default architecture — the only platform that simultaneously solves for high frequency, low power, high integration, low cost, and high-volume manufacturability.

In summary, TSEM's OFC 2026 announcement articulates a comprehensive answer to the optical transceiver industry's most pressing bottleneck: how to produce high-performance, power-efficient, next-generation optical interconnects at the scale and cost points demanded by the AI infrastructure supercycle. SiGe + SiPho, manufactured on 300mm silicon with 85%+ yields and at one-third the cost of InP, is that answer — and TSEM, with its dominant market share, locked-in customers, and aggressive capacity build, is the company delivering it.

It is almost for certain that by the time of SpaceX's large Space DC deployment in 2028-2030, 400G per lane is a must. TSEM has great potential given all its five core advantages: High Frequency, Low power, High integration, Low cost, and mass production ramp up flexibility. Two other alternatives, InP EML (shortage, expensive, and low frequency) has a big disadvantage, and latest material TFLN Thin Film Lithium Niobate, is yet to be proven and able to sustain in the space environment soon.

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